Next: Conditional 'case', Main: Supported Constructs, Previous: Initial Statement

Conditional 'if-else-if' Statement

Both languages support the conditional `if statement' and the translation is mostly straightforward, with a few exceptions. In Verilog, the result of an `if expression' can be (0,1,X,Z). In VHDL, the `if expression' has to decode to the boolean type in VHDL (FALSE, TRUE). All Verilog expressions do not map directly to VHDL. A typical example is the following `if expression' :

	if (a)

There is no direct equivalent in VHDL, because the above `if expression' tests if `a' is `1', in the case `a' is a register data type, or if `a' has a value other than `0', if `a' is an integer type. To preserve logical equality during translation, Verilog2VHDL translates a non-boolean `if expression' in Verilog to a boolean expression by using a VHDL function that returns a boolean value. Resulting VHDL is:

	IF to_boolean(a) THEN