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Compiler Directives

Verilog supports numerous compiler directives. In this version of Verilog2VHDL, only the `timescale and `define compiler directives are supported. `define compiler directives are translated as system - wide generic declarations i.e. all modules following the `define statement have a generic interface list corresponding to the `define statement. The time unit specified with the `timescale directive is used as the time unit in VHDL.

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