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There are no direct VHDL equivalents to Verilog system tasks or functions, so the translation is done
by automatically creating equivalent procedures in the VHDL output file. Of all Verilog system tasks
and functions, Verilog2VHDL supports those associated with formatted output ($display, $fdisplay,
$strobe, $fstrobe, $write, $fwrite), memories ($readmemb, $readmemh), files ($fopen, $fclose) and functions
such as $time, $rtoi, $itoa.