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Supported and Unsupported Constructs

The following enumerations are supported by version 3.0 of Verilog2VHDL. New features are tagged with a ** .

Data types
- Supported
  - wire specification
  - ** tri specification
  - ** supply0 specification
  - ** supply1 specification
  - memory declaration
  - integer declaration
  - time declaration
  - real declaration
  - reg specification
  - parameter declaration
- Not Supported
  - nettype(s) tri1, wand, triand, tri0, supply1, wor, trior, trireg
  - expandrange for net declaration
  - charge strength for net declaration
  - drive strength for net declaration
  - delay specification for net declaration

Expressions

Supported

operand types : net, register, net bit-select, register bit-select

binary logical operators:

 ||, &&, !=, ==

binary relational operators:

 <, <=, >, >=

operand types : number, time, integer, net part-select, register part-select

operators:

{}, arithmetic operators, modulus, !, ===, 

!==, <<, >>, ?:

unary operators:

 &, ~&, |, ~|, ^, 

~^ or ^~

Continuous Assignments
- Supported
  - Left hand side : net (vector or scalar), constant bit select of vector net
  - Delays of type (rising) only, can be of (min/typ/max) type
  - Left hand side : constant part select of vector net, concatenation
  - Net declaration Assignment
- Not Supported
  - drive strength
  - delays of type (rising, falling, turnoff)
Procedural Assignments
- Supported
  - Left hand side : register (vector or scalar), constant bit select of vector register
  - Blocking procedural assignment
  - Non-blocking procedural assignment
  - Delays of type min/typ/max
  - Left hand side : constant part select of vector register, memory element, concatenation
- Not Supported
  - procedural continuos assignment
Gate and Switch Level
- Supported
  - gate type: and, nand, nor, or, xor, xnor, buf, not, bufif0, bufif1, notif0, notif1
  - Delays of type (rising) only, can be of (min/typ/max) type
- Not Supported
  - gate type: nmos, pmos, cmos, rnmos, rpmos, rcmos, tran, tranif0, tranif1, rtran, rtranif0, pullup, pulldown
  - drive strength
  - delays of type (rising, falling, turnoff)
Behavioral Modeling
- Supported
  - always statement
  - initial statement
  - conditional if-else-if
  - case statement
  - for statement
  - casex, casez statements
  - forever, repeat, while
  - Sequential Blocks
  - tasks
  - functions
- Not Supported
  - named events
  - parallel blocks
Hierarchical Structures
- Supported
  - module
  - Ports: input, output, inout
  - Module instantiation
  - named port connection with concatenated names
  - Macromodule
- Not Supported
  - Hierarchical names
Compiler Directives
- Supported
  - `timescale
  - `define
- Not Supported
  - all others
System Tasks and Functions
- Supported
  - $display
  - $fdisplay
  - $write
  - $fwrite
  - $strobe
  - $fstrobe
  - $readmemh
  - $readmemb
    - Supported
      - %b %d format specification
      - std_logic, std_logic_vector, integer type
      - $readmem functions: 1 entry per line in memory data file; only '//' type of comments
    - Not Supported
      - Type conversions for std_logic, std_logic_vector, integer types
      - $readmem functions: multiple entries per line in memory data file; '/* */' type of comments
  - $time
  - $itor
  - $rtoi
- Not Supported
  - all other system tasks
  - all other system functions