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Next: Memory Declaration,
Main: Supported Constructs, Previous:
Parameter Declarations
Register and Net Declaration
There are two main types of data types in Verilog: Registers and Nets. Registers are a data type to
model data storage. They can hold their value until the next assignment. Nets, on the contrary, do not
store any value (except trireg), and instead take the value of the driving gate or assignment. They
are primarily used to represent connections between structural entities. VHDL models both registers
and nets using the type signal. Signals in VHDL are used both for electrical connections and
storing values.
Special Note: Register declarations and other Verilog declarations inside user defined tasks and functions are modeled as VHDL variables. |
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