SYNAPTICADcolon TRANSLATION SERVICES V2V

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Integer Declaration

One of the types allowed in Verilog is the Integer type. Integer types in Verilog are translated to a resolved subtype of the pre-defined integer type in VHDL.

Special Note: The resolved subtype v2v_integer, and type integer_array are declared in the v2v_types package available in the types.vhd file.