SynaptiCAD Tutorials
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Timing Diagram Editor 1: Basic Drawing and Timing Analysis
(TD) 1.1 Timing Diagram Editor Choices
(TD) 1.2 Set the Base and Dispaly Time Unit
(TD) 1.3. Add the Clock
(TD) 1.4 Add the Signals
(TD) 1.5 Drawing Signal Waveforms
(TD) 1.6 Editing Signal Waveforms
(TD) 1.7 Adjust Diagram to Match Figure
(TD) 1.8 Add the D Flip-Flop Propagation Delay
(TD) 1.9 Add the Inverter Propagation Delay
(TD) 1.10 Add the Setup for the Dinput to Clock
(TD) 1.11 Add a Free Parameter
(TD) 1.12 Drawing with Equations
(TD) 1.13 Drawing Virtual Busses
(TD) 1.14 Drawing Group Buses and Differential Signals
(TD) 1.15 Working with Drawing Environnment
(TD) 1.16 Summary
Timing Diagram Editor 2: Simulated Signals
(TD) 2.1 Setup for Simulation
(TD) 2.2 Simulate a Boolean Equation
(TD) 2.3 Boolean Equations with Delays
(TD) 2.4 Register and Latch Signals
(TD) 2.5 Set and Clear Lines
(TD) 2.6 Multi-bit Equations
(TD) 2.7 Design a Multi-Bit Counter
(TD) 2.8 End Diagram Marker Stops Simulation
(TD) 2.9 Behavioral HDL Code
(TD) 2.10 Simulated Bus Signals
(TD) 2.11 Summary of Simulated Signals Tutorial
Timing Diagram Editor 3: Display and Documentation
(TD) 3.1 Setup for the Tutorial
(TD) 3.2 Parameter Display Strings
(TD) 3.3 Repeat Parameters Across the Diagram
(TD) 3.4 Move Parameters to Different Signals
(TD) 3.5 Adjust Parameter Vertical Placement
(TD) 3.6 Curved Parameters
(TD) 3.7 Clock Jitter and Display
(TD) 3.8 Marker Time Compression
(TD) 3.9 Marker Snap to Edge
(TD) 3.10 Marker Loops and Pipelines
(TD) 3.11 Spacers and Text Font Controls
(TD) 3.12 Highlight Regions with Text Objects
(TD) 3.13 Text and Hidden Signals
(TD) 3.14 Summary of Display and Documentation Tutorial
Timing Diagram Editor 4: Analog Signals
(TD) 4.1 Viewing Analog Waveforms
(TD) 4.2 Faster Drawing with Waveform Equation Blocks
(TD) 4.3 Writing Python Waveform Equation Blocks
(TD) 4.4 State Label Equation Alternative
(TD) 4.5 Drawing a Step Signal
(TD) 4.6 Generating Sine Waves
(TD) 4.7 Generating Capacitor Charge and Discharge
(TD) 4.8 Generating Ramp Waveforms
(TD) 4.9 Random Analog Equations
(TD) 4.10 Exporting to SPICE, VHDL, and Verilog
(TD) 4.11 ADC and DAC Conversion
(TD) 4.12 Summary of Analog Signals Tutorial
Timing Diagram Editor 5: Parameter Libraries
(TD) 5.1 Setup for Library Tutorial
(TD) 5.2 Add Libraries to the "Library Search List"
(TD) 5.3 Setup the Library Specifications
(TD) 5.4 Investigate Preferences Dialog
(TD) 5.5 Referencing Parameters in Libraries
(TD) 5.6 Using Macros to Examine Tradeoffs Between Different Libraries
(TD) 5.7 Parameter Libraries Summary
Timing Diagram Editor 6: Advanced Modeling and Simulation
(TD) 6.1 Set up a New Timing Diagram
(TD) 6.2 Generate the Clock, Draw Waveforms, & Use Waveform Equations
(TD) 6.3 Modeling State Machines
(TD) 6.4 Checking for Simulation Errors
(TD) 6.5 Incremental Simulation
(TD) 6.6 Modeling Combinational Logic
(TD) 6.7 Entering Direct HDL Code for Simulated Signals
(TD) 6.8 Modeling n-bit Gates
(TD) 6.9 Incorporating Pre-written HDL Models into Waveformer Simuations
(TD) 6.10 Modeling the Incrementor and Latch Circuit
(TD) 6.11 Modeling Tri-State Gates
(TD) 6.12 Debugging External Verilog Models
(TD) 6.13 Verify the Histogram Circuit
(TD) 6.14 Controlling the Length of the Simulation
(TD) 6.15 Editing Verilog Source Files
(TD) 6.16 Simulating Your Model with Traditional Verilog Simulators
(TD) 6.17 Summary
Test Bench Generation 1: VHDL-Verilog Stimulus
(TBench) 1.1 Load the Tutorial Timing Diagram
(TBench) 1.2 Hex and Binary State Values
(TBench) 1.3 Export a Verilog Test Bench
(TBench) 1.4 Signal Data Types and VHDL user defined types
(TBench) 1.5. Export a VHDL Test Bench
(TBench) 1.6 Summary of VHDL-Verilog Stimulus Tutorial
Test Bench Generation 2: Reactive Test Bench Option
(TBench) 2.1 Run Program with Reactive Test Bench Option
(TBench) 2.2 Create a Project to hold the MUT
(TBench) 2.3 Extract Signal Names and setup the Clock
(TBench) 2.4 Draw Stimulus Waveforms and Export Test Bench
(TBench) 2.5 Draw Expected Waveform and Wait for the Assertion
(TBench) 2.6 Draw a Read Cycle and Verify the read
(TBench) 2.7 Add a Sample to Verify Data Read from MUT
(TBench) 2.8 Drive Waveform Values using a File
(TBench) 2.9 Create For-Loop to Perform Multiple Writes and Reads
(TBench) 2.10 Alternate Test Bench Designs
(TBench) 2.11 Summary of Reactive Test Bench Tutorial
Test Bench Generation 3: TestBencher Pro Basic Tutorial
(TBench) 3.1 Run TestBencher Pro
(TBench) 3.2 Create a Project
(TBench) 3.3 Add the SRAM model to the Project
(TBench) 3.4 Setup the Template Diagram
(TBench) 3.5 Create the Write Cycle Transaction Diagram
(TBench) 3.6 Create the Read Cycle Transaction Diagram
(TBench) 3.7 Add a Sample to Verify Data
(TBench) 3.8 Create the Initialize Transaction Diagram
(TBench) 3.9 Add Transaction Calls to the Sequencer Process
(TBench) 3.10 Setup the Simulator
(TBench) 3.11 Generate the Test Bench and Simulate
(TBench) 3.12 Examine Report Window Results
(TBench) 3.13 Examine the Stimulus and Results Diagram
(TBench) 3.14 TestBencher Pro Basic Tutorial Summary
Test Bench Generation 4: TestBencher Pro with Random Transactions
(TBench) 4.1 Run TestBencher Pro
(TBench) 4.2 Setup the VHDL Simulator
(TBench) 4.3 Load the RandomizedSweepTest Project
(TBench) 4.4 Weight the Transaction Types
(TBench) 4.5 Post Random Transaction Types
(TBench) 4.6 Constrain the Random Data
(TBench) 4.7 Simulate and View the Results
(TBench) 4.8 Set the Random Seed
(TBench) 4.9 Randomize Transactions Summary
Simulation 1: VeriLogger Basic Verilog Simulation
(Sim) 1.1 Simulator Choices
(Sim) 1.2 Add Files to the Project
(Sim) 1.3 Build the Tree and Investigate the Project
(Sim) 1.4 Simulate the Project
(Sim) 1.5 Prepare for Graphical Test Bench Generation
(Sim) 1.6 Draw Test Bench in Debug Run Mode
(Sim) 1.7 Simulate in Auto Run Mode
(Sim) 1.8 Breakpoints, Stepping and Inspecting
(Sim) 1.9 Archiving Stimulus and Results
(Sim) 1.10 Saving the Project files
(Sim) 1.11 Summary of VeriLogger Basic Verilog Simulation
Simulation 2: Using WaveFormer with ModelSim VHDL
(Sim) 2.1 Compile SynaptiCAD Library Models
(Sim) 2.2 Create a project and extract the ports
(Sim) 2.3 Draw the test bench waveforms
(Sim) 2.4 Export Waveforms to VHDL
(Sim) 2.5 Simulate VHDL test bench using ModelSim
(Sim) 2.6 Compare simulation results against expected results
(Sim) 2.7 Summary of Using WaveFormer with ModelSim VHDL
Waveform Comparison Tutorial
(Compare) 1: Setup for using Compare
(Compare) 2: Individual Compare Signals
(Compare) 3: Experiment with Tolerance
(Compare) 4: Compare Timing Diagrams
(Compare) 5: Set All Compare Signal Properties
(Compare) 6: Find the Differences
(Compare) 7: Perform a Clocked Comparison
(Compare) 8: Compare During Clock Cycle Windows
(Compare) 9: Mask Sections to Exclude Comparison
(Compare) 10: Don't Care Regions
(Compare) 11: Adjust the Time Difference Between Two Diagrams
(Compare) 12: Summary of the Comparison Tutorial
Gigawave and WaveViewer Viewer Tutorial
(Viewer) 1: Converting a vcd file into a btim file
(Viewer) 2: Importing a subset of the Waveforms
(Viewer) 3: Creating a Filter File to selectively load signals
(Viewer) 4: Show and Hide Signals in the display
(Viewer) 5: Searching for Signal Names or States
(Viewer) 6: Options: Gigawave, Waveform Comparison,Transaction Tracking
(Viewer) 7: Waveviewer/GigaWave Viewer Tutorial Summary
SDC Timing Generation Tutorial
(SDC) 1: Setup Project and Create Timing Diagram
(SDC) 2: Enter Master Clocks
(SDC) 3: Enter Derived Clocks
(SDC) 4: Sketching the Waveforms
(SDC) 5: Signal Direction
(SDC) 6: Add Delays to Inputs
(SDC) 7: Add Setups and Holds to Outputs
(SDC) 8: VCD Simulation Files Generate SDC
(SDC) 9: Summary
Transaction Tracker Tutorial
(TT) 1: Open the Example File
(TT) 2: Match all occurrences of a simple pattern
(TT) 3: Match Consecutive Occurrences with Concatenation Operator
(TT) 4: Match with consecutive repetition Operator
(TT) 5: Match with non-consecutive Repetition Operator
(TT) 6: Bit-slices and the Boolean operators
(TT) 7: Implication operator
(TT) 8: Implication Next-Cycle operator
(TT) 9: PSL Property
(TT) 10: Summary of Transaction Tracker Tutorial
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